In signal processing systems, fetching instructions and data from memory is often a slow process compared to the operating frequency of the master device that has initiated the fetch instruction. Consequently, if the system is running a large number of such fetch operations, it can cause a significant decrease in the overall system performance. It is known to implement pre-fetching schemes, whereby data and/or instructions are fetched in advance of the master device initiating a fetch instruction for them. As a result the performance impact of accessing relatively slow memory elements may be reduced.
However, a problem with implementing such prefetching schemes is that it is not always possible to accurately ‘predict’ the instructions and/or data that a master device is going to require, and the timing thereof, and as such unnecessary prefetch operations are often performed. Performing such unnecessary prefetches can hinder system performance, since they use up system resources in order to be performed, especially where flash memory access requests are non-abortable. Accordingly, inappropriate configuration of such prefetching schemes may render their effectiveness as, at best, sub-optimal, or even detrimental to the system performance.